A methodology for hardware verification based on logic simulation

A Methodology for Hardware Veri cation Based on Logic Simulation

1991 Abstract A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulllling the system speciication will produce a particular response to a sequence of simulation commands. This style of veriication has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the low-level details of...

A Design Methodology for Reliable MRF-Based Logic Gates

Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based met...

A Methodology for Large-Scale Hardware Verification

We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities undertaken in large-scale verification efforts and to structure the associated code and proof-script artifacts. The methodology deploys a combination of model checking and lightweight theorem proving in higher-order logic, tightly...

vlogsl: A Strategy Language for Simulation-Based Verification of Hardware

Verification Methodology for Heterogeneous Hardware/Software Systems

Modern electronic systems are constituted by heterogeneous elements, e.g. hardware/software, and are typically embedded. The complexity of this kind of systems is such, that traditional validation techniques, like simulation and testing, are not enough to verify the correctness of these systems. In consequence, new formal verification techniques that overcome the limitations of traditional vali...